R10000_LLSC_WAR    21 arch/mips/include/asm/mach-cavium-octeon/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-generic/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    24 arch/mips/include/asm/mach-ip22/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-ip27/war.h #define R10000_LLSC_WAR			1
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-ip28/war.h #define R10000_LLSC_WAR			1
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-ip32/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-malta/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    56 arch/mips/include/asm/mach-pmcs-msp71xx/msp_regops.h #define R10000_LLSC_WAR 0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-pmcs-msp71xx/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-rc32434/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    24 arch/mips/include/asm/mach-rm/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    35 arch/mips/include/asm/mach-sibyte/war.h #define R10000_LLSC_WAR			0
R10000_LLSC_WAR    20 arch/mips/include/asm/mach-tx49xx/war.h #define R10000_LLSC_WAR			0