PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 5537 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 5647 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000
PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK  887 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK                                                   0x04000000L