PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 5555 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 5665 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff
PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK  900 drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK                                                    0x01FFFFFFL