PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK  154 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK  154 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL