PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT  151 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT  151 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4