PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK  155 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK  155 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h #define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L