PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 18360 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK 0x30000
PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK  357 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PPLL_MODE_CNTL__reg_tmg_pwr_state_MASK                                                                0x00030000L