PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 18382 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK 0x400
PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK  386 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PPLL_FREQ_CTRL3__reg_tmg_fcw_sel_MASK                                                                 0x00000400L