PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 18366 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK 0xffff
PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK  366 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PPLL_FREQ_CTRL1__reg_tmg_fcw1_frac_MASK                                                               0x0000FFFFL