PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 18486 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK 0xf0
PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK  496 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PPLL_DFT_CNTL__regs_pw_obs_clk_sel_1_MASK                                                             0x000000F0L