PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 3548 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 4986 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 5178 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 4166 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 5286 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 5190 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8