PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 11598 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 11410 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0
PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 8400 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000
PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 2048 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0