PLLU_HW_PWRDN_CFG0_SEQ_ENABLE  220 drivers/clk/tegra/clk-pll.c #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
PLLU_HW_PWRDN_CFG0_SEQ_ENABLE  209 drivers/clk/tegra/clk-tegra210.c #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE		BIT(24)