PLL               496 drivers/clk/clk-stm32f4.c 	PLL,
PLL              1156 drivers/clk/clk-stm32mp1.c #define PLL(_id, _name, _parent, _flags, _offset)\
PLL               918 drivers/clk/mediatek/clk-mt2701.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
PLL              1189 drivers/clk/mediatek/clk-mt2712.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL              1169 drivers/clk/mediatek/clk-mt6779.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
PLL               634 drivers/clk/mediatek/clk-mt6797.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL                45 drivers/clk/mediatek/clk-mt7622.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL                45 drivers/clk/mediatek/clk-mt7629.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL               596 drivers/clk/mediatek/clk-mt8135.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
PLL              1045 drivers/clk/mediatek/clk-mt8173.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL              1094 drivers/clk/mediatek/clk-mt8183.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
PLL               756 drivers/clk/mediatek/clk-mt8516.c #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
PLL               119 drivers/clk/pistachio/clk.h #define PLL(_id, _name, _pname, _type, _reg, _rates)		\
PLL               295 drivers/clk/rockchip/clk.h #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,	\
PLL               270 drivers/clk/samsung/clk.h #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable)	\
PLL               104 drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h #define	PLL			0x2	/* main chip pll */