PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT   92 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT   92 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 3345 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT                                                       0x1c
PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 8248 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c
PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT   92 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c