PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT   64 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT   64 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT   64 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 3323 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT                                                       0x1c
PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 8208 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c
PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT   64 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c