PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT   52 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT   52 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT   52 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d
PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 8194 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d
PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT   52 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d