PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT   36 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT   36 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT   36 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 3301 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT                                                       0x1c
PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 8168 drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c
PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT   36 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c