PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 6455 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x00000004
PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 7688 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4
PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 8270 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB1_TX_LANE5_SCI_STAT_OVRD_REG0__TXMARG_5__SHIFT 0x4