PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 5096 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000L
PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 6543 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000
PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 7077 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB1_RX_GLB_CTRL_REG5__RX_CFG_TERM_MODE_GEN3_MASK 0x20000000