PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 4840 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x00000300L
PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 6425 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_PLL_LC1_SCI_STAT_OVRD_REG0__PLL_LC1_FREQMODE_MASK 0x300