PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 4439 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x00000010
PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 9292 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_PIF_SC_CTL__SC_LANE_0_RESUME__SHIFT 0x10