PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 4430 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L
PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 9271 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20