PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 3958 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x00000400L
PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 9075 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_PIF_CNTL__PLL_BINDING_ENABLE_MASK 0x400