PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 3793 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x00000018
PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 5964 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG3__MODE_10__SHIFT 0x18