PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 3764 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x00300000L
PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 5929 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG2__MODE_5_MASK 0x300000