PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 3733 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x00000010
PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 5896 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_GLB_SCI_STAT_OVRD_REG1__MODE_0__SHIFT 0x10