PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 3632 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L
PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 5825 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 6331 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB1_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600