PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 3265 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x00000000
PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 5252 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0
PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 5788 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB0_TX_LANE1_SCI_STAT_OVRD_REG0__TXPWR_1__SHIFT 0x0