PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 2866 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x00001000L
PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 5113 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000
PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 5651 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB0_TX_GLB_OVRD_REG1__TX_CFG_TCLK_DIV_OVRD_EN_MASK 0x1000