PB0_PIF_SC_CTL__SC_PHASE_1_MASK 1422 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x00000100L
PB0_PIF_SC_CTL__SC_PHASE_1_MASK 8313 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_PIF_SC_CTL__SC_PHASE_1_MASK 0x100