PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 1413 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x00000015
PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 8340 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_PIF_SC_CTL__SC_LANE_5_RESUME__SHIFT 0x15