PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 1382 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x00000020L
PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 8309 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0_MASK 0x20