PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 1384 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x00000010L
PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 8307 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_PIF_SC_CTL__SC_ENTER_L1_FROM_L0S_MASK 0x10