PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK  906 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x00000008L
PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 8099 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_PIF_CNTL__PHYCMD_CR_EN_MODE_MASK 0x8