PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 686 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x00300000L PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 3611 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_1_MASK 0x300000