PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK  684 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x00030000L
PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 3607 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_GLB_SCI_STAT_OVRD_REG1__MODE_0_MASK 0x30000