PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK  584 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x00000600L
PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 3537 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600
PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 3987 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_RO_REG_VREF_SEL_MASK 0x600