PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK  582 drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x00000180L
PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 3535 drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180
PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 3985 drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h #define PB0_GLB_CTRL_REG3__BG_CFG_LC_REG_VREF1_SEL_MASK 0x180