PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 24310 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 16918 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 18249 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 18126 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 6965 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x00000015
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 5760 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 6548 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 7082 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15