PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 7512 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 1948 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 1806 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 1803 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 6375 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x0000000a
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 6566 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 7354 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 7890 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa