PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 7542 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 1978 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 1836 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 1833 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 6374 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000400L
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 6565 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 7353 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 7889 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400