PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 7622 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 2048 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 1904 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 1919 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 7948 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0