PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 22870 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 15473 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 16804 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 16676 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 5697 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x00000000
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 5636 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 6424 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 6958 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0