PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 24410 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 17016 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 18347 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 18224 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 5659 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x00000001
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 5536 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 6324 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 6858 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1