PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 24409 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 17015 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 18346 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 18223 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 5655 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x00000000
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 5534 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 6322 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 6856 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0