PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 24411 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 17017 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 18348 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 18225 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 5649 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x00000002
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 5538 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 6326 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 6860 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2