PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 1633 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT                                                              0x5
PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 1459 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT                                                              0x5
PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 5621 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x00000005
PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 5676 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 6464 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 6998 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5