PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 7136 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 1622 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 1485 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 1448 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0