PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 24261 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 16871 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 18202 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 18077 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 5591 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x00000004
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 5574 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 6362 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 6896 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4